1. Field of the Invention
The present invention relates to a monitoring method for a three dimensional integrated circuit (3D IC), and in particular relates to a monitoring method for Through Silicon Vias (TSVs) of 3D ICs.
2. Background
As the semiconductor fabrication technology develops, need for smaller electronic devices increases. The type one-chip-per-package which is often applied in traditional IC process.
FIG. 1 shows an outside view diagram of stacked ICs in the prior art. In FIG. 1, the ICs 102 are connected with the lead frame 106 via the leads 104. Taking a metal oxide semiconductor field effect transistor (MOSFET) for example, for deep submicron MOSFETs, RC delay occurs, due to the smaller dimensions of the leads 104; which seriously effects performance of the deep submicron MOSFETs. Thus, three dimensional integrated circuit (3D IC) have been disclosed to reduce RC delay.
FIG. 2A shows an outside view diagram of a 3D IC. The 3D IC 200 comprises a plurality of ICs 202. The ICs 202 are stacked in the 3D space to shorten the total wire length to reduce RC delay. FIG. 2B shows an inside structure diagram of the 3D IC. Within the 3D IC 200, Through-Silicon Vias (TSVs) are disposed throughout, connecting the plurality of ICs 202 therein. Fabrication of TSVs is critical for performance of deep submicron ICs.
For TSV manufacturing, pilot holes of a certain dimension are fabricated on the IC 202 and then filled with a suitable conducting material. However, there is no efficient method to determine whether the TSVs meet manufacturing standards. Therefore, a simple and efficient monitoring method for Through Silicon Vias (TSVs) of 3D ICs is called for.